1. Field of the Invention
The present invention relates generally to data processing systems and more particularly to apparatus for performing diagnostic testing on a microprogrammed commercial instruction processor.
2. Description of the Prior Art
As the semiconductor industry induces more complex and higher speed logic elements, data processing systems designed using these elements perform more complex logic functions and have higher systems throughout than data processing systems designed in the past. Many of the data processing systems are made up of microprogram controlled subsystems coupled in common to a system bus. Diagnostic testing systems have been developed for such microprogrammed data processing systems to check out each of the subsystems coupled to the system bus from a central source. U.S. Pat. No. 4,159,534 entitled "Firmware/Hardware System for Testing Interface Logic of a Data Processing System" describes a typical diagnostic test. This type of diagnostic test unfortunately makes it difficult to isolate a particular error. It is possible that the error is caused by a malfunction of the central source: the system bus, a subsystem that was not addressed, or a subsystem that was addressed.
Microprogrammed subsystems are designed with the capability to perform diagnostic tests independently of the remainder of the data processing system to which the subsystems are coupled. U.S. Pat. No. 4,019,033 entitled "Control Store Checking System and Method" describes a diagnostic system which verifies that the parity logic associated with each register tested has valid parity. This type of diagnostic tests the parity of each register in turn which receives predetermined data. Also the diagnostic does not force bad parity into the system to assure that the bad parity is detected.
U.S. Pat. No. 3,566,093 entitled "Diagnostic Method and Implementation for Data Processors" describes the use of the parity error signal in a diagnostic routine for signalling erroneous access to a memory location or to provide a distinctive synchronization signal for test equipment while the memory is aided through a loop including locations under test.
U.S. Pat. No. 3,518,413 entitled "Apparatus for Checking the Sequencing of a Data Processing System" describes a diagnostic system in which a count of a number of cycles for a microprogram to reach a particular state is compared with the actual count on the number of cycles it took to reach that state.
U.S. Pat. No. 3,831,148 entitled "Nonexecute Test Apparatus" describes self-testing of a processing system under microinstruction control using parity checking apparatus.
U.S. Pat. No. 4,048,481 entitled "Diagnostic Testing Apparatus and Method" describes apparatus which is operative to condition data recovery to receive blocks of synchronization and data patterns arranged in a predetermined format to simulate data transfer from a peripheral device.
U.S. Pat. No. 4,038,537 entitled "Apparatus for Verifying the Integrity of Information Stored in a Data Processing System Memory" describes apparatus for adding together a column of bits including a parity bit in each bit location of a memory having a plurality of word locations, and comparing each sum with a predetermined parity bit of a parity word in one of the word locations.
It should be understood that the references cited herein are those of which the applicants are aware and are presented to acquaint the reader with the level of skill in the art and may not be the closest reference to the invention. No representation is made that any search has been conducted by the applicants.